Multi-formalism in Different Levels of Abstraction for Requirements Engineering and Architectural Design of Real-Time Embedded Systems

Abstract

Real-time embedded systems (RTES) are increasingly omnipresent in human activities. The reliability and accuracy with which these systems are developed have a predominant impact when dealing with system operation. Thus, the success in the development of these systems relates not only to the accurate computational execution itself, but also how reliably real-time embedded constraints are developed. Requirement Engineering and architectural design of RTES are challenging activities, since they deal with complex and diversified domains such as software, hardware, mechanical, electronics, electrical and the physical environment. Requirements specification and architectural design, associated with the RTES domain, must attend to embedded and functional system requirements and their related non-functional concerns, while considering cost, quality, reliability and safety properties. This thesis relates to the development and analysis of a methodology that covers different phases of RTES design. Different strategies for analyzing timing constraints are proposed in such a way that they are evaluated at different abstraction levels, such as early analysis of requirement models and empirical evaluation of architectural models assumptions. Initially, constructors, stereotypes and enumerations of the MARTE profile are traced and linked to specific and non-functional concerns of the RTES domain. Through the collected data and the combined use of the SysML profile, Timed Automata and SPES guidelines the MARTeSys^{ReqD} methodology is proposed. The proposed methodology employs Model-Driven Systems Engineering approaches and presents distinctive guidelines to design RTES based on viewpoints, refinements, granularity levels, annotation and verification of real-time embedded concerns. Furthermore, the proposed methodology provides new strategies to formally describe architectural design decisions, to measure the design complexity of RTES, as well as to validate timing constraints from the early model requirement viewpoint. The methodology proposed in this study is both quantitatively and qualitatively validated, which aims at demonstrating the expressiveness and contributions made toward RTES development.